(1) Field of the Invention
The invention relates to an integrated circuit device, and, more particularly, to a method to decouple switching current noise from a power supply of an integrated circuit device.
(2) Description of the Prior Art
Very high-speed integrated circuit devices present many design challenges. For example, synchronized switching of a large number of circuits, as with a very high-speed clock, can create very large switching currents. Referring now to FIG. 1, an exemplary integrated circuit block 10 is illustrated. The circuit block 10 is connected to power supply VDD 14 and ground 18. The circuit block 10 comprises a large number of logic circuits capable of very high-speed operation. During normal operation, internal circuit nodes, such as NODE224 and NODE326 will switch states as synchronized by the system clock CLK 19. At any time, a large number of nodes may be switching. In addition, if a very high-speed clock frequency is used, then the switching speeds must be very fast. Where both a high switching speed and a high switching rate occur at the same time, a large switching current IVDD 28 is drawn on the VDD 14 line. These large switching currents can cause a substantial amount of switching noise to be coupled onto the VDD line 14 as shown. In very high-speed integrated circuit devices, VDD 14 is often set to a very low value of about 1V. A large switching noise can cause the circuit 10 to malfunction at such a low operating voltage level.
Referring now to FIG. 2, it has been found in the prior art that the addition of capacitance between the power supply VDD 32 and ground VSS 34 of an integrated circuit 30 can reduce the effect of switching current. High frequency components of the switching noise are shunted from VDD 32 to VSS 34 through a decoupling capacitance CD5 36. Referring now to FIG. 3, a particular form of decoupling capacitance CD 44 from VDD 40 to VSS 42 is shown. CD 44 may comprise a MOS device such as a polysilicon-oxide-silicon gate. In this case, the decoupling capacitor CD 44 is cascaded through a resistor RD 46. Referring now to FIG. 4, an alternative form of the decoupling capacitor from VDD 40 to VSS 42 is illustrated. In this case, one PMOS device P147 and one NMOS device N148 are cascaded. Each device P147 and N148 acts as both a capacitor and a resistor.
Referring now to FIG. 5, yet another approach to the decoupling capacitor is illustrated. In this case, a MOS capacitor 62 and a MOS transistor 64 are connected in series between VDD 72 and ground 74. It is observed in the art that, as process technology shrinks to sub-0.13 micron, MOS gate leakage current becomes a serious problem. This leakage occurs because a very thin gate oxide layer 70 is used between the polysilicon 66 and the substrate 50 or n-well 54 to form the gates 62 and 64. At the same time, the supply voltage for a sub-0.13 micron process is typically about 1 Volt while the operating frequency is very high. Therefore, a large decoupling capacitance, perhaps as large as the total gate capacitance of the circuit, is required to suppress switching noise on the supply VDD 72. Unfortunately, when very large decoupling capacitors 62 are formed using MOS gates, the large gate leakage can cause an unacceptable current drain on the circuit. In addition, the large gate area of the decoupling capacitors 62 is a likely location for a gate defect that can cause the capacitor to be shorted.
It is found in the prior art that the series connected MOS transistor 64 may be used as a switch to shut OFF the decoupling capacitor 62 connection to ground 74. In particular, the decoupling capacitor 62 may be tested for excessive leakage during power-up. If excessive leakage is detected, then the MOS switch 64 is shut OFF during all circuit operation. In any case, after power-up, the MOS switch 64 is controlled by a static signal 76.
Several prior art inventions relate to methods to decouple switching current noise from a power supply of an integrated circuit device. U.S. Pat. No. 5,506,457 to Krauter et al and U.S. Pat. No. 6,307,250 B1 to Krauter et al teach a circuit to detect a defective decoupling capacitor during a power-up test. The defective capacitor is switched out of the circuit. U.S. Pat. No. 5,789,964 to Voldman shows a method to detect a defective decoupling capacitor during power-up and to switch in a capacitor during an ESD event. U.S. patent application Ser. No. 2002-0081832 A1 to Bernstein et al describes a circuit to test decoupling capacitors in an integrated circuit device. If a decoupling capacitor fails, then a fuse is blown to disable a grounding switch. Finally, in the article, “Interconnect and Circuit Modeling Techniques for Full-Chip Power Supply Noise Analysis,” by Chen et al, in IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, Vol. 21, No. 3, August. 1998, pp. 209-215, a capacitor and switch combination is described.